Method and apparatus for efficient register-transfer level...

Details Method and apparatus for efficient register-transfer level... Method and apparatus for efficient register-transfer level...

2006-11-07

2006-11-07

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

07134100

ABSTRACT:
Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

REFERENCES:
patent: 5742814 (1998-04-01), Balasa et al.
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6735744 (2004-05-01), Raghunathan et al.
patent: 2003/0208723 (2003-11-01), Killian et al.

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