Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-07
2006-02-07
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S013000, C382S145000
Reexamination Certificate
active
06996790
ABSTRACT:
A two-dimensional yield map for a device, such as an integrated circuit, in a fabrication facility is computed and associated with layout data for the device in a hierarchical and/or instance-based layout file. The device has a layout including a pattern characterizable by a combination of members of a set of basis shapes. A set of basis pre-images include yield map data representing an interaction of respective members of the set of basis shapes with a defect model. A yield map for the pattern is created by combining basis pre-images corresponding to basis shapes in the combination of members that characterize the pattern to provide a combination result. The output may be displayed as a two dimensional map to an engineer performing yield analysis, or otherwise processed.
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Garbowski Leigh M.
Kenta Suzue Haynes Beffel & Wolfeld LLP
Synopsys Inc.
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