Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-06-20
2006-06-20
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S216000, C257S410000, C257S411000
Reexamination Certificate
active
07064052
ABSTRACT:
A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.
REFERENCES:
patent: 5057463 (1991-10-01), Bryant et al.
patent: 5244843 (1993-09-01), Chau et al.
patent: 5374578 (1994-12-01), Patel et al.
patent: 5486488 (1996-01-01), Kamiyama
patent: 5508221 (1996-04-01), Kamiyama
patent: 5663088 (1997-09-01), Sandhu et al.
patent: 5726083 (1998-03-01), Takaishi
patent: 5728603 (1998-03-01), Emesh et al.
patent: 5817581 (1998-10-01), Bayer et al.
patent: 5840368 (1998-11-01), Ohmi
patent: 5926741 (1999-07-01), Matsuoka et al.
patent: 6046494 (2000-04-01), Brigham et al.
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6066581 (2000-05-01), Chivukula et al.
patent: 6114258 (2000-09-01), Miner et al.
patent: 6124154 (2000-09-01), Miyasaka
patent: 6184155 (2001-02-01), Yu et al.
patent: 6197668 (2001-03-01), Gardner et al.
patent: 2001/0020725 (2001-09-01), Okuno et al.
Wolf, et al. Silicon Processing for the VLSI Era, vol. 1-Process Technology, Lattice Press: Sunset Beach CA, 1986, pp. 57-58.
Van Zant, Microchip Fabrication, 4th ed. McGraw-Hill: New York, 1984, p. 172.
Ghandi, VLSI Fabrication Principles, John Wiley & Sons: New York, 1994, p. 465.
Ghandi, VLSI Fabrication Principles, 2nd ed., John Wiley & Sons: New York, 1994, pp. 466-470.
Lu, et al., “Leakage Current Comparison Between Ultra-Thin Ta2O5films and conventional gate dielectrics” IEEE Electron Device Letters 19(9), Sep. 1998, pp. 341-342.
Alers, et al., “Intermixing at the Tantalum Oxide/Silicon Interface in Gate Dielectric Structures” Applied Physics Letters 73(11), Sep. 14, 1998, pp. 1517-1519.
Luan, et al. “Ultra-thin High Quality Ta2O5Dielectric Prepared by In-Situ Rapid Thermal Processing” Electron Devices Meeting, held Dec. 6-9, 1998, IEDM '98 Technical Digest, pp. 609-612.
Al-Shareef Husam N.
DeBoer Scott J.
Gealy Dan
Weimer Ronald A.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Rodgers Colleen E.
Schillinger Laura M.
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