Method for optimal use of direct fit and interpolated models...

Details Method for optimal use of direct fit and interpolated models... Method for optimal use of direct fit and interpolated models...

2006-08-08

2006-08-08

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07089512

ABSTRACT:
A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits. The method further comprises schematically simulating a custom circuit; back annotating to a schematic circuit which of the transistors use direct-fit models and which of the transistor devices are interpolated; determining whether the transistor devices are in any of cutoff, saturation, static linear, and dynamic linear mode during simulation of the custom circuit; removing the saturation and dynamic linear mode transistor devices; back annotating the netlist to a schematic with a predetermined device state; and performing sensitivity analysis on saturation and dynamic linear mode transistor devices.

REFERENCES:
patent: 6212490 (2001-04-01), Li et al.
patent: 6345235 (2002-02-01), Edgecombe et al.
patent: 2004/0044510 (2004-03-01), Zolotov et al.
patent: 2004/0181761 (2004-09-01), Kidera

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