Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-06-06
2006-06-06
Pham, Hoai (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000
Reexamination Certificate
active
07056822
ABSTRACT:
An interconnect structure and fabrication method are provided to form air gaps between interconnect lines and between interconnect layers. A conductive material is deposited and patterned to form a first level of interconnect lines. A first dielectric layer is deposited over the first level of interconnect lines. One or more air gaps are formed in the first dielectric layer to reduce inter-layer capacitance, intra-layer capacitance or both inter-layer and intra-layer capacitance. At least one support pillar remains in the first dielectric layer to promote mechanical strength and thermal conductivity. A sealing layer is deposited over the first insulative layer to seal the air gaps. Via holes are patterned and etched through the sealing layer and the first dielectric layer. A conductive material is deposited to fill the via holes and form conductive plugs therein. Thereafter, a conductive material is deposited and patterned to form a second level of interconnect lines.
REFERENCES:
patent: 5668398 (1997-09-01), Havemann et al.
patent: 5711987 (1998-01-01), Bearinger et al.
patent: 5750415 (1998-05-01), Gnade et al.
patent: 5751056 (1998-05-01), Numata
patent: 5792706 (1998-08-01), Michael et al.
patent: 5798559 (1998-08-01), Bothra et al.
patent: 5923074 (1999-07-01), Jeng
patent: 6017814 (2000-01-01), Grill et al.
patent: 6040248 (2000-03-01), Chen et al.
patent: 6054769 (2000-04-01), Jeng
patent: 6057224 (2000-05-01), Bothra et al.
patent: 6059553 (2000-05-01), Jin et al.
patent: 6087729 (2000-07-01), Cerofolini et al.
patent: 6211561 (2001-04-01), Zhao
Farjami & Farjami LLP
Newport Fab LLC
Pham Hoai
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