Injection enhanced gate transistor including second emitter...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29198

Reexamination Certificate

active

07095079

ABSTRACT:
An injection enhanced gate transistor includes a drift layer, a collector layer and a base layer divided into main cell regions and dummy cell regions by a plurality of trenches formed to extend from the top surface of the base layer into the drift layer. The main cell has a first emitter layer selectively formed in the surface layer of the base layer, gate electrodes formed in the trenches, and an emitter electrode located over the base layer. The dummy cell has a second emitter layer selectively formed so as to be scattered in the surface layer of the base layer and have a surface area smaller than that of the first emitter layer to prevent waveform vibration associate with negative gate capacitance.

REFERENCES:
patent: 2003/0042525 (2003-03-01), Tanaka
patent: 2003-204066 (2003-07-01), None
U.S. Appl. No. 09/853,661, filed May 14, 2001, Tanaka.
U.S. Appl. No. 10/230,119, filed Aug. 29, 2002, Tanaka.
U.S. Appl. No. 10/354,048, filed Jan. 30, 2003, Yamaguchi et al.
U.S. Appl. No. 10/437,060, May 14, 2003, Tanaka.
U.S. Appl. No. 10/677,260, filed Oct. 2003, Tanaka et al.
U.S. Appl. No. 10/814,246, filed Apr. 1, 2004, Okuno et al.
I. Omura, et al., IEEE Transactions on Electron Devices, vol. 46, No. 1, pp. 237-244, “Oscillation Effects in IGBT's Related to Negative Capacitance Phenomena”, Jan. 1999.
I. Omura, et al., Proceedings of ISPSD, pp. 25-28, “IEGT Design Concept Against Operation Instability and its Impact to Application”, May 25, 2000.

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