Image processing system, and semiconductor device and...

Electrical computers and digital data processing systems: input/ – Access arbitrating – Access prioritizing

Reexamination Certificate

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Details

C710S113000

Reexamination Certificate

active

07007124

ABSTRACT:
A data processing system includes: at least one function module connected to a single system bus; a data transfer controller which outputs a first bus use permission request signal based on a data transfer request signal output from the at least one function module; a central processing unit connected to the system bus which outputs a second bus use permission request signal; an arbitration controller for determining, based on the first and second bus use permission request signals, which of the data transfer controller and the central processing unit should obtain a permission to use the system bus; a section for setting a first data amount which can be continuously transferred by the at least one function module; a section for suspending an output of the first bus use permission request signal to the arbitration controller for at least one clock cycle after a data transfer by the at least one function module is completed; and a section for giving the permission to use the system bus to one of the data transfer controller and the central processing unit in such a manner that the data transfer controller has a priority over the central processing unit during a period when the first bus use permission request signal is being issued.

REFERENCES:
patent: 5517325 (1996-05-01), Shimatani
patent: 5930488 (1999-07-01), Mitsuishi
patent: 6320573 (2001-11-01), Stephenson
patent: 2003/0142219 (2003-07-01), McGarvey et al.
patent: 56-27429 (1981-03-01), None
patent: 62-24348 (1987-02-01), None
patent: 63-29867 (1988-02-01), None
patent: 63-261451 (1988-10-01), None
patent: 4-7773 (1992-01-01), None
patent: 8-171528 (1996-07-01), None
patent: A11120123 (1999-04-01), None

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