Method and apparatus for reducing capacitive load-related...

Details Method and apparatus for reducing capacitive load-related... Method and apparatus for reducing capacitive load-related...

2006-02-14

2006-02-14

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C323S271000, C323S275000, C323S283000, C323S285000, C327S108000, C327S109000

Reexamination Certificate

active

07000128

ABSTRACT:
The present invention increases power efficiency in power FET applications with varying loads. A constant frequency mode can be used without detracting from efficiency. This is accomplished by reducing repetitive gate charge power losses. The present invention controls the channel impedance of the FET using a timed tri-state driver to drive a level of charge associated with the gate of the FET that is appropriate to the load requirements. When the voltage level at the FET gate reaches the appropriate level, the driver is tri-stated, so that the gate does not continue to charge.

REFERENCES:
patent: 5352932 (1994-10-01), Tihanyi
patent: 5973367 (1999-10-01), Williams
patent: 6285173 (2001-09-01), Bentolila et al.
patent: 6335715 (2002-01-01), Lee
patent: 6407514 (2002-06-01), Glaser et al.
patent: 6441673 (2002-08-01), Zhang
patent: 6778001 (2004-08-01), Mayama et al.

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