Method and apparatus for lowering bus clock frequency in a...

Details Method and apparatus for lowering bus clock frequency in a... Method and apparatus for lowering bus clock frequency in a...

2006-08-15

2006-08-15

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S300000, C713S320000, C713S322000, C713S323000, C713S500000, C713S600000, C327S100000, C327S113000, C327S297000, C710S110000, C710S113000, C710S117000, C710S305000, C710S313000, C714S034000, C714S814000

Reexamination Certificate

active

07093153

ABSTRACT:
A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

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