Processor system using synchronous dynamic memory

Details Processor system using synchronous dynamic memory Processor system using synchronous dynamic memory

2006-11-28

2006-11-28

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C713S400000

Reexamination Certificate

active

07143230

ABSTRACT:
A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

REFERENCES:
patent: 4394753 (1983-07-01), Penzel
patent: 4513372 (1985-04-01), Ziegler et al.
patent: 4727477 (1988-02-01), Gavril
patent: 4796232 (1989-01-01), House
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5243699 (1993-09-01), Nickolls et al.
patent: 5283877 (1994-02-01), Gastinel et al.
patent: 5287327 (1994-02-01), Takasugi
patent: 5339276 (1994-08-01), Takasugi
patent: 5339399 (1994-08-01), Lee et al.
patent: 5367494 (1994-11-01), Shebanow et al.
patent: 5371896 (1994-12-01), Gove et al.
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5539911 (1996-07-01), Nguyen et al.
patent: 5574876 (1996-11-01), Uchiyama et al.
patent: 6334166 (2001-12-01), Uchiyama et al.
patent: 0245882 (1987-11-01), None
patent: 0339224 (1989-11-01), None
patent: 0468480 (1992-01-01), None
patent: 5781660 (1982-05-01), None
patent: 58-166579 (1983-10-01), None
patent: 61220056 (1986-09-01), None
patent: 62-128342 (1987-06-01), None
patent: 62-165247 (1987-07-01), None
patent: 62180398 (1987-11-01), None
patent: 6-476342 (1989-03-01), None
patent: 02029988 (1990-01-01), None
patent: 3-15956 (1991-01-01), None
patent: 3-238539 (1991-10-01), None
L. Johnson et al., “System Level ASIC Design For Hewlett-Packard's Low Cost PA-RISC Workstations”, International Conference of Computer Design Proceedings, pp. 132-133, 1991.
Hitachi IC Memory Handbook 2, DRAM, DRAM Module, 389-393, 1991.
Nikkei Electronics, 1992, pp. 143-147.
Speed System Memory by Interleaving DRAM Acceses, 2326 Electronic Design, 37, 1989, No. 21, Cleveland, Ohio.
Nikkei Electronics, No. 553, pp. 143-147, May 11, 1992 (English language translation).
N. Mekhiel, “Speed System Memory By Interleaving DRAM Accesses DRAM Performs at SRAM Speeds To Keep Up With A 33.Mhz 68030 Running In Burst Mode”, Electronic Design, vol. 37, No. 21, Oct. 12, 1989, pp. 65-68, 70, 72.
D. Bursky, “80X86-Compatible Family Outperforms Original CPUs”, Electronic Design, vol. 39, No. 18, Sep. 26, 1991, pp. 53-56, 61.
Talmudi et al., “A 100MPIS, 64b Superscalar Microprocessor with DSP Enhancements,” ISSCC 91, Session 5, Microprocessors, Paper TA 5.6,IEEE, NY, 1991.

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