Semiconductor device

Details Semiconductor device Semiconductor device

2006-06-27

2006-06-27

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S349000, C257S350000, C257S351000, C257S374000, C257S466000, C257S618000

Reexamination Certificate

active

07067881

ABSTRACT:
A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

REFERENCES:
patent: 5889331 (1999-03-01), Bai
patent: 6314021 (2001-11-01), Maeda et al.
patent: 6512258 (2003-01-01), Maeda
patent: 6518155 (2003-02-01), Chau et al.
patent: 6765273 (2004-07-01), Chau et al.
patent: 6777283 (2004-08-01), Maeda
patent: 6777759 (2004-08-01), Chau et al.
patent: 2002/0053711 (2002-05-01), Chau et al.
patent: 10-209167 (1998-08-01), None
Y. Hirano, et al., IEEE International SOI Conference, pp. 131-132, “Bulk-Layout-Compatible 0.18μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)”, Oct. 1999.
S. Maeda, et al., Symposium on VLSI Technology Digest of Technical Papers, pp. 154-155, “Impact of 0.18μm SOI CMOS Technology Using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF/Analog Applications”. 2000.
Y. Hirano, et al., IEEE, IEDM, pp. 467-470, “Impact of 0.10 μm SOI CMOS With Body-Tied Hybrid Trench Isolation Structure to Break Through the Scaling Crisis of Silicon Technology”, 2000.
S. Maeda, et al., Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials, pp. 270-271, “A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide”, 2001.

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