Interface circuit for selectively latching between different...

Details Interface circuit for selectively latching between different... Interface circuit for selectively latching between different...

2006-02-14

2006-02-14

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C711S104000, C365S189011

Reexamination Certificate

active

07000139

ABSTRACT:
An interface circuit includes a frequency divider which divides a frequency of a base clock to provide frequency-divided clock signals; a first address register which stores an address signal at a timing in which the frequency-divided clock signal is turned to high; a second address register which stores the address signal at a timing in which the clock signal is turned to low; a first data register which stores a data signal at a timing in which the clock signal is turned to high; and a second data register which stores the data signal at a timing in which the clock signal is turned to low. The data signals stored in the first and second data registers are selectively outputted.

REFERENCES:
patent: 4298954 (1981-11-01), Bigelow et al.
patent: 5926475 (1999-07-01), Saldinger et al.
patent: 6724686 (2004-04-01), Ooishi et al.
patent: 6754740 (2004-06-01), Happonen
patent: 6801979 (2004-10-01), Estakhri

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