Software controllable register map

Details Software controllable register map Software controllable register map

2006-06-20

2006-06-20

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

Reexamination Certificate

active

07065631

ABSTRACT:
Virtual registers are mapped to architectural or physical registers according to a register map that is configurable with software. In one embodiment, only privileged software can configure the register map. In another embodiment, a portion of the register map is configurable with non-privileged software, and another portion is only configurable with privileged software. In yet another embodiment the register map is fully configurable by user software. The configurable register map provides backwards compatibility to code written for hardware-defined register mapping, while allowing flexible approaches to register mapping in code generated for a processor architecture using a software controllable register map.

REFERENCES:
patent: 2003/0074545 (2003-04-01), Uhler
Yang et al., Latte: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, IEEE, Oct. 12-16, 1999, pp. 128-138.
David L. Weaver and Tom Germond,The Sparc Architecture Manual, Version 9, Prentice Hall, 9, 5,-21, 29-60, 87-129, 247-282 (1994).

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