Method for fomring a self-aligned LTPS TFT

Details Method for fomring a self-aligned LTPS TFT Method for fomring a self-aligned LTPS TFT

2006-06-20

2006-06-20

Sarkar, Asok Kumar (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257SE21412, C257SE21435, C257SE21632, C257SE21704

Reexamination Certificate

active

07064021

ABSTRACT:
A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the substrate. Then, a source electrode, a drain electrode, and lightly doped drains (LDD) of the NLTPS TFT are formed. Further, gate electrodes of the NLTPS TFT and the PLTPS TFT are formed on the gate insulating layer. Finally, the gate electrode of the PLTPS TFT is utilized to form a source electrode and a drain electrode in the active layer of the PLTPS TFT.

REFERENCES:
patent: 5604139 (1997-02-01), Codama et al.
patent: 6197626 (2001-03-01), Yamazaki et al.
patent: 6225150 (2001-05-01), Lee et al.
patent: 6541793 (2003-04-01), Ohnuma et al.
patent: 2005/0250264 (2005-11-01), Hotta et al.

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