Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2006-06-20
2006-06-20
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S230030
Reexamination Certificate
active
07064991
ABSTRACT:
A semiconductor storage device includes command decoder for decoding an input command to output a decoded result and for simultaneously outputting A and B bank activation signal for activating said first and second banks, during a parallel test; a set of bank A control circuits for generating a control signal for a bank A based on a bank A activating signal, a selector circuit receiving a bank B activation signal output from the command decoder and the control signal for a bank A, for selecting outputting a bank B activating signal during the normal operation and for selecting and outputting the control signal for a bank A during parallel test, and a set of bank B control circuits receiving the output from the selector circuit to generate a control signal for the bank B.
REFERENCES:
patent: 6134145 (2000-10-01), Wong
patent: 6636448 (2003-10-01), Koshikawa
patent: 11-45599 (1999-02-01), None
patent: 11-242632 (1999-09-01), None
“Method for Using SDRAM”, Chapter 7, Basic Operation Mode, p. 56-60, Internet, Aug. 4, 2003, Elpida Memory <URL>http.//www.elpida.com/pdfs/JO123N50.pdf.
Elpida Memory Inc.
McGinn IP Law Group PLLC
Nguyen Van-Thu
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