Method and apparatus for delineating data in an FEC-coded...

Details Method and apparatus for delineating data in an FEC-coded... Method and apparatus for delineating data in an FEC-coded...

2006-12-19

2006-12-19

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S777000

Reexamination Certificate

active

07152199

ABSTRACT:
One embodiment of the present invention provides a system that facilitates construction of a forward error correction (FEC) coded Ethernet frame. The system generates a number of FEC parity bits for the conventional Ethernet frame and inserts a start sequence before the conventional Ethernet frame. Next, the system appends an even- or odd-delimiter to the conventional Ethernet frame. The even-delimiter and the odd-delimiter are selected such that there is a sufficiently large Hamming distance between them, thereby reducing the probability of mistaking the even-delimiter for the odd-delimiter, or mistaking the odd-delimiter for the even-delimiter, if bit error occurs.

REFERENCES:
patent: 5956102 (1999-09-01), Lane
patent: WO03/092207 (2002-04-01), None
“Extensions of the Reconciliation Sublayer (RS) and Physical Coding Sublayer (PCS)/ Physical Media Attacment (PMA) for 1000BSE-X for Multi-Point Links and Forward Error Correction”, IEEE Draft P802.3ah, Apr. 19, 2004, copyright 2004 IEEE, pp. 528 to 558.
“Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer, type 1000BASE-X”, Local and Metropolitan Area Networks, IEEE Std. 802.3-2002, Section Three, copyright 2002 IEEE, pp. 32 to 78.

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