Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-06-20
2006-06-20
Nadav, Ori (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S588000, C438S592000, C257S059000, C257S072000, C257S347000, C257S350000
Reexamination Certificate
active
07064020
ABSTRACT:
A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective doping to form a low-concentration impurity region which adjoins a channel forming region, and a sub-region overlapped by the gate electrode and a sub-region not overlapped by the gate electrode, to also mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing.
REFERENCES:
patent: 3933529 (1976-01-01), Goser
patent: 4963504 (1990-10-01), Huang
patent: 5015599 (1991-05-01), Verhaar
patent: 5034791 (1991-07-01), Kameyama et al.
patent: 5182619 (1993-01-01), Pfiester
patent: 5247190 (1993-09-01), Friend et al.
patent: 5323042 (1994-06-01), Matsumoto
patent: 5399502 (1995-03-01), Friend et al.
patent: 5412240 (1995-05-01), Inoue et al.
patent: 5482871 (1996-01-01), Pollack
patent: 5508216 (1996-04-01), Inoue
patent: 5532175 (1996-07-01), Racanelli et al.
patent: 5543340 (1996-08-01), Lee
patent: 5543947 (1996-08-01), Mase et al.
patent: 5567966 (1996-10-01), Hwang
patent: 5581092 (1996-12-01), Takemura
patent: 5594569 (1997-01-01), Konuma et al.
patent: 5608251 (1997-03-01), Konuma et al.
patent: 5616506 (1997-04-01), Takemura
patent: 5620905 (1997-04-01), Konuma et al.
patent: 5623157 (1997-04-01), Miyazaki et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5658815 (1997-08-01), Lee et al.
patent: 5686328 (1997-11-01), Zhang et al.
patent: 5693959 (1997-12-01), Inoue et al.
patent: 5719588 (1998-02-01), Johnson
patent: 5757048 (1998-05-01), Inoue
patent: 5763285 (1998-06-01), Yang
patent: 5767930 (1998-06-01), Kobayashi et al.
patent: 5773330 (1998-06-01), Park
patent: 5841170 (1998-11-01), Adan et al.
patent: 5858820 (1999-01-01), Jung et al.
patent: 5903249 (1999-05-01), Koyama et al.
patent: 5912492 (1999-06-01), Chang et al.
patent: 5923961 (1999-07-01), Shibuya et al.
patent: 5923962 (1999-07-01), Ohtani et al.
patent: 5981367 (1999-11-01), Gonzalez
patent: 6160279 (2000-12-01), Zhang et al.
patent: 6165824 (2000-12-01), Takano et al.
patent: 6166396 (2000-12-01), Yamazaki
patent: 6180957 (2001-01-01), Miyasaka et al.
patent: 6198133 (2001-03-01), Yamazaki et al.
patent: 6259120 (2001-07-01), Zhang et al.
patent: 6259138 (2001-07-01), Ohtani et al.
patent: 6259144 (2001-07-01), Gonzalez
patent: 6281552 (2001-08-01), Kawasaki et al.
patent: 6285042 (2001-09-01), Ohtani et al.
patent: 6335541 (2002-01-01), Ohtani et al.
patent: 6365933 (2002-04-01), Yamazaki et al.
patent: 6469317 (2002-10-01), Yamazaki et al.
patent: 6501098 (2002-12-01), Yamazaki
patent: 6617644 (2003-09-01), Yamazaki et al.
patent: 2002/0163049 (2002-11-01), Yamazaki et al.
patent: 2003/0054653 (2003-03-01), Yamazaki et al.
patent: 2003/0122132 (2003-07-01), Yamazaki
patent: 2004/0051142 (2004-03-01), Yamazaki et al.
patent: 0 602 250 (1994-06-01), None
patent: 0 650 197 (1995-04-01), None
patent: 1 001 467 (2000-05-01), None
patent: 1 003 223 (2000-05-01), None
patent: 2 077 993 (1981-12-01), None
patent: 04-369271 (1992-12-01), None
patent: 05-102483 (1993-04-01), None
patent: 5-188401 (1993-07-01), None
patent: 07-130652 (1995-05-01), None
patent: 07-202210 (1995-08-01), None
patent: 08-78329 (1996-03-01), None
patent: 10-135468 (1996-05-01), None
patent: 10-092576 (1998-04-01), None
patent: 10-135469 (1998-05-01), None
patent: 10-247735 (1998-09-01), None
patent: WO/13148 (1990-11-01), None
Specification and Drawings for U.S. Appl. No. 09/441,025, Filed: Nov. 16, 1999 “Method of Manufacturing Semiconductor Devices”.
Specification and Drawings for U.S. Appl. No. 09/441,026, Filed: Nov. 16, 1999 “Electro-Optical Device and Manufacturing Method Thereof”.
Hatano et al., “A Novel Self-Aligned Gate-Overlapped LDD Poly-Sci TFT with High Reliability and Performance”, IEDM Technical Digest, 1997, pp. 523-526.
Furue et al., “P-78: Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability”, SID 98 Digest, pp. 782-785.
Yoshida et al., “33.2: A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time”, SID 97 Digest, pp. 841-844.
Inui et al., “Thresholdhess Antiferroelectricity in Liquid Crystals and its Application to Displays”, J. Mater Chem., vol. 6, No. 4, 1996, pp. 671-673.
Terada et al., “Half-V Switching Mode FLCD”, Proceedings of the 46thApplied Physics Association Lectures, 28P-V-8, Mar. 1999, p. 1316.
Yoshihara, “Time Division Full Color LCD by Ferroelectric Liquid Crystal”, EKISHO, vol. 3, No. 3, 1999, pp. 190-194.
Schenk et al., “Polymers for Light Emitting Diodes”, EuroDisplay '99 Proceedings, Sep. 6-9, 1999, pp. 33-37.
European Search Report dated Oct. 1, 2004 Application No. 99 12 3427.
Costellia Jeffrey L.
Nadav Ori
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
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