Dual-thickness active device layer SOI chip structure

Details Dual-thickness active device layer SOI chip structure Dual-thickness active device layer SOI chip structure

2006-11-28

2006-11-28

Flynn, Nathan J. (Department: 3663)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000

Reexamination Certificate

active

07141855

ABSTRACT:
A dual-thickness active device layer SOI chip structure is provided. The SOI chip structure has an active device layer, at least one oxide region located at a predetermined position of the active device layer and with a first predetermined depth, at least one trench surrounding the oxide region and having a second predetermined depth greater than the first predetermined depth, and a ground layer connected to the active device layer and the oxide region. The SOI structure further has a first silicon-based wafer and a second wafer. Both wafers are bonded together by wafer bonding. At least two different active device layer thicknesses exist to meet requirements of a wide variety of SOI devices placed thereon, with the setting of the oxide region filled with thermal oxide or other oxide variations.

REFERENCES:
patent: 6563173 (2003-05-01), Bolam et al.
patent: 6570217 (2003-05-01), Sato et al.
patent: 2002/0153911 (2002-10-01), Cho et al.
patent: 2002/0175378 (2002-11-01), Choe et al.
patent: 2005/0189589 (2005-09-01), Zhu et al.

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