Method and apparatus for implementing multiple column...

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S189020, C365S230030

Reexamination Certificate

active

07064990

ABSTRACT:
An apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements. At least one spare memory element is configured at a size corresponding to one of the subcolumn elements. An input redundancy multiplexing stage and an output redundancy multiplexing stage are configured for steering around one or more defective memory array elements, and an input bit decoding stage and an output bit decoding stage are configured for implementing an additional, external multiplexing stage with respect to the input redundancy multiplexing stage and the output redundancy multiplexing stage.

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