System and method for reducing design cycle time for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07062740

ABSTRACT:
A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

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patent: 6075934 (2000-06-01), Chiluvuri et al.
patent: 6446250 (2002-09-01), Becker
patent: 6457157 (2002-09-01), Singh et al.
patent: 6550047 (2003-04-01), Becker
patent: 6829753 (2004-12-01), Lee et al.

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