Semiconductor device with upper portion of plugs contacting...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Reexamination Certificate

active

07061032

ABSTRACT:
A semiconductor device including: a cell transistor including: a pair of source and drain regions formed in a surface portion of a silicon substrate so as to have a predetermined space therebetween; a channel region sandwiched by the source and drain regions; a gate formed above the channel region with a gate dielectric film being formed therebetween; and a silicon plug formed on the silicon substrate, the silicon plug electrically contacting the source and drain regions, an upper portion of the silicon plug being a first self-aligned silicide portion.

REFERENCES:
patent: 5475240 (1995-12-01), Sakamoto
patent: 5567962 (1996-10-01), Miyawaki et al.
patent: 6087706 (2000-07-01), Dawson et al.
patent: 6096644 (2000-08-01), Lukanc
patent: 6114209 (2000-09-01), Chu et al.
patent: 6436770 (2002-08-01), Leung et al.
patent: 6461959 (2002-10-01), Chien et al.
patent: 6632723 (2003-10-01), Watanabe et al.
patent: 6873539 (2005-03-01), Fazan et al.
Kedzierski et al., Design analysis of thin-boby silicide source/drain devices, 2001 IEEE International SOI conference, pp. 21-22.
Inoh et al., FBC (Floating Body Cell) for Embedded DRAM on SOI, 2003 Symposium on VLSI Technology Digest of technical Papers, pp. 63-64.

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