Semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S296000, C257SE27104

Reexamination Certificate

active

07138674

ABSTRACT:
A semiconductor memory device includes a cell block composed of several series-connected units having a ferroelectric capacitor and a cell transistor parallel-connected to the ferroelectric capacitor and a select transistor connected to an end of the cell block. Mutually separated first impurity diffusion layers are formed on the surface of the semiconductor substrate along a first direction, and have a first area. A second impurity diffusion layer is formed on the surface of the semiconductor substrate separated from the end first impurity diffusion layer, and has a second area. A first gate electrode is provided on the semiconductor substrate between the first impurity diffusion layers along a second direction. A second gate electrode is provided on the semiconductor substrate between the end first impurity diffusion layer and the second impurity diffusion layer along a second direction. A contact electrically connects a bit line and the second impurity diffusion layer.

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patent: 5617349 (1997-04-01), Koike
patent: 5903492 (1999-05-01), Takashima
patent: 2002/0027798 (2002-03-01), Takashima
patent: 2002/0123203 (2002-09-01), Dehm et al.
patent: 7-335738 (1995-12-01), None
patent: 8-36888 (1998-02-01), None
patent: 10-255483 (1998-09-01), None
patent: 2000-156472 (2000-06-01), None
patent: 2002-197856 (2002-07-01), None
patent: 1998-069790 (1998-10-01), None

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