Method and apparatus for evaluating and debugging assertions

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000

Reexamination Certificate

active

07143373

ABSTRACT:
Roughly described, assertion expressions are evaluated against the binary signal values of a circuit simulation in such a way as to be able to report status information at intermediate levels of assertion subexpressions. In one embodiment, the status information reported for an intermediate subexpressions contains the final status of that subexpression in response to a given assertion attempt, at least to the extent it has been determined by the end of the evaluation period (e.g. pass, fail or indeterminate). In another embodiment, the status information reported for an intermediate subexpression contains a tick-by-tick analysis of the activity within that subexpression. In another embodiment, the status information for a subexpression can also contain a tick-by-tick analysis of the activity of an operator of the subexpression. Other kinds and levels of detail at the subexpression level can be provided in various other embodiments.

REFERENCES:
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 6247165 (2001-06-01), Wohl et al.
patent: 6591402 (2003-07-01), Chandra et al.
“Smart Verification with VCS 7.0”, Synopsys Inc., Apr. 2003, Mountain View, CA.
“VCS Complete RTL Verification Solution”, Synopsys Inc. Data Sheet, 2004, Mountain View, CA.
Synopsys VCS Observed Coverage Technology, Synopsys Inc., 2002, Mountain View, CA.
“Assertion-Based Verification”, Synopsys Inc., Mar. 2003, Mountain View, CA.
Fitzpatrick, Tom, “Assertions in System Verilog: A Unified Language for More Efficient Verification”, Synopsys Inc., Oct. 2003.
“@HDL Updates Products for SystemVerilog and PSL”, Press release, Nov. 17, 2003, pp. 1-4, Milpitas, CA.
Maliniak, David, “Assertion-Based Verification Smoothes the Road to IP Reuse”, http://www.elecdesign.com/Articles/Print.cfm?ArticleID=2748, visited Jan. 29, 2004, available at Electronic Design Online ID #2748, Sep. 16, 2002.
“SystemVerilog 3.1 Accellera's Extensions to Verilog”, Accellera Organization, Inc., 2002, Napa, CA.
“Verilog Hardware Description Language Reference Manual (LRM), Version 1.0”, Open Verilog International, Nov. 1991, Sunnyvale, CA.
“Standard Vital ASIC Modeling Specification, Draft, IEEE 1076.4/DI”, Institute of Electrical and Electronics Engineers, Inc., Apr. 2000, New York, N. Y.
IEEE Standard VHDL Language Reference Manual, 2000, Piscataway, N. J.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for evaluating and debugging assertions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for evaluating and debugging assertions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for evaluating and debugging assertions will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3671136

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.