Ferroelectric memory device and read control method thereof

Details Ferroelectric memory device and read control method thereof Ferroelectric memory device and read control method thereof

2006-06-20

2006-06-20

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189110

Reexamination Certificate

active

07064972

ABSTRACT:
A ferroelectric memory device is disclosed, which includes a memory cell array which is formed of a matrix layout of memory cells each having a transistor with its gate connected to a word line and a ferroelectric capacitor having one end connected to a bit line and the other end connected to a plate line, a plate-line drive circuit for driving the plate line, a word-line drive circuit for driving the word line, and a sense amplifier connected to the bitline for detecting and amplifying memory cell data. At least one of the plateline drive circuit and said wordline drive circuit has a pullup circuit operable to potentially raise or boost an output terminal of this at least one circuit from a low level up to a high level and a pulldown circuit for letting the output terminal potentially drop from the high level down to the low level. At least one of the pullup and pulldown circuits is arranged to be variable in driving ability or “drivability” during its driving operation.

REFERENCES:
patent: 5903492 (1999-05-01), Takashima
patent: 6977835 (2005-12-01), Kang
D. Takashima, et al., ISSCC, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 40-41, “A 76mm28Mb Chain Ferroelectric Memory”, Feb. 5, 2001.
U.S. Appl. No. 10/934,358, filed Sep. 7, 2004, Oikawa et al.

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