Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-08-15
2006-08-15
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S197000, C438S201000, C438S257000, C438S261000, C438S501000, C438S506000, C438S720000, C257S270000, C257S316000, C257S324000, C257S411000
Reexamination Certificate
active
07091130
ABSTRACT:
A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
REFERENCES:
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6320784 (2001-11-01), Muralidhar et al.
patent: 6444545 (2002-09-01), Sadd et al.
patent: 6958265 (2005-10-01), Steimle et al.
patent: 7015090 (2006-03-01), Okazaki et al.
patent: 2004/0135204 (2004-07-01), Wang et al.
patent: 2004/0212019 (2004-10-01), Shinohara
patent: 2005/0098822 (2005-05-01), Mathew
S., Wolf, Silicon Processing for the VLSI Era, vol. 4, Lattice Press Press (2002) pp. 385-386.
Cavins et al., “A Nitride-Oxide Blocking Layer for Scaled SONOS Non-Volatile Memory,”Motorola, Inc., Jan. 10, 2002, 5 pages.
Cavins et al., “Integrated Stacked Gate Oxide and Interpoly Oxide,”Motorola, Inc.,, Nov. 1996, pp. 93-94.
Attorney Docket No. SC13087TP filed concurrently.
U.S. Appl. No. 10/987,047, filed Nov. 12, 2004.
Chindalore Gowrishankar L.
Muralidhar Ramachandran
Rao Rajesh A.
Steimle Robert F.
Angadi Maki
Freescale Semiconductor Inc.
King Robert L.
Noonan Michael P.
Norton Nadine
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