Method of interconnecting die and substrate

Details Method of interconnecting die and substrate Method of interconnecting die and substrate

Filed on

2006-10-17

Date issued

2006-10-17

Examiner

Whitehead, Jr., Carl (Department: 2813)

Patent Class

Semiconductor device manufacturing: process

SubClass

Packaging or treatment of packaged semiconductor

SubSubClass

Assembly of plural semiconductive substrates each possessing...

Other Related Categories

C438S106000, C257S778000, C257S779000

Type

Reexamination Certificate

Status

active

Patent number

07122403

Description

ABSTRACT:
A low resistance package-to-die interconnect scheme for reduced die stresses includes a relatively low melting temperature and yield strength solder on the die and a relatively higher melting temperature and electrically conductive material such as copper on the substrate. A soldered joint connects the solder to the electrically conductive material to couple/connect the die and substrate to one another. The soldered joint is formed by heating the die and solder thereon to at least the melting temperature of the solder and thereafter contacting the molten solder with the conductive material on the substrate, which is at a substantially lower temperature for minimizing residual stress from soldering due to coefficient of thermal expansion mismatch between the substrate and die.

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