Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2006-10-24
2006-10-24
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000, C365S189011, C365S230010, C365S230050, C365S230060
Reexamination Certificate
active
07126372
ABSTRACT:
Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.
REFERENCES:
patent: 5586299 (1996-12-01), Wakerly
patent: 5774474 (1998-06-01), Narayanan et al.
patent: 5999480 (1999-12-01), Ong et al.
patent: 6034542 (2000-03-01), Ridgeway
patent: 6191614 (2001-02-01), Schultz et al.
patent: 6201728 (2001-03-01), Narui et al.
patent: 6204687 (2001-03-01), Schultz et al.
patent: 6255848 (2001-07-01), Schultz et al.
patent: 6255849 (2001-07-01), Mohan
patent: 6262596 (2001-07-01), Schultz et al.
patent: 6304101 (2001-10-01), Nishihara
patent: 6326806 (2001-12-01), Fallside et al.
patent: 6349346 (2002-02-01), Hanrahan et al.
patent: 6429682 (2002-08-01), Schultz et al.
patent: 6605960 (2003-08-01), Veenstra et al.
patent: 6732354 (2004-05-01), Ebeling et al.
patent: 6836839 (2004-12-01), Master et al.
patent: 6851047 (2005-02-01), Fox et al.
patent: 6907595 (2005-06-01), Curd et al.
patent: 2002/0138716 (2002-09-01), Master et al.
patent: 2003/0034848 (2003-02-01), Norman et al.
patent: 2003/0105949 (2003-06-01), Master et al.
patent: 2003/0154357 (2003-08-01), Master et al.
patent: 2004/0030736 (2004-02-01), Scheuermann
patent: 2004/0078403 (2004-04-01), Scheuermann et al.
patent: 2005/0044344 (2005-02-01), Stevens
patent: EP 0 748 051 (1996-12-01), None
U.S. Appl. No. 10/377,857, filed Feb. 28, 2003, Blodget et al.
U.S. Appl. No. 10/683,944, filed Oct. 10, 2003, Young.
U.S. Appl. No. 10/806,697, filed Mar. 22, 2004, Voogel et al.
U.S. Appl. No. 10/836,960, filed Apr. 30, 2004, Vadi et al.
U.S. Appl. No. 10/836,961, filed Apr. 30, 2004, Vadi et al.
U.S. Appl. No. 10/837,330, filed Apr. 30, 2004, Vadi et al.
U.S. Appl. No. 10/837,331, filed Apr. 30, 2004, Goetting et al.
Xilinx, Inc.; DS031; “Virtex-II 1.5V Field-Programmable Gate Arrays”; Advance Product Specification; Oct. 2, 2001; (v1.7); available from Xilinix, Inc, 2100 Logic Drive San Jose, California 95124; pp. 37, 90, and 387.
Xilinx, Inc.; Virtex-II Platform FPGA Handbook; Dec. 3, 2001; available from Xilinx, Inc., 2100 Logic Drive San Jose, California 95124; p. 387.
Raphael David et al.; “DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints”; Copyright 2002 IEEE; pp. 1-8.
Raphael David et al,; “DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints”; Copyright 2002 IEEE; pp. 1-8.
Collins Anthony
Goetting F. Erich
Logue John D.
McGrath John
Schultz David P.
Tan Vibol
Webostad W. Eric
Xilinx , Inc.
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