Nonvolatile semiconductor memory device having controlled charge

Details Nonvolatile semiconductor memory device having controlled charge Nonvolatile semiconductor memory device having controlled charge

1995-06-01

1997-04-15

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518911, 36518526, 36518529, G11C 700

Patent

active

056216890

ABSTRACT:
It is postulated that a nonvolatile semiconductor memory device of the present invention includes a charge pump. The nonvolatile semiconductor memory device includes a memory cell array unit having a plurality of memory transistors formed therein to store data. Each memory transistor has a drain region connected to a predetermined bit line BL which is connected to a write circuit. A charge pump is connected to the write circuit. A predetermined potential is applied to a memory transistor via the write circuit by this charge pump in a writing mode. A charge pump load control means for suppressing variation in the charge pump load is connected to a memory transistor or a well region in which the memory transistor is formed. Thus, the charge pump load can be stabilized to allow improvement of the writing or erasing characteristics of the nonvolatile semiconductor memory device.

REFERENCES:
patent: 5243559 (1993-09-01), Murai
patent: 5343423 (1994-08-01), Shimoji
patent: 5379253 (1995-01-01), Bergemont
patent: 5406524 (1995-04-01), Kawamura et al.
"A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory", H. Onoda et al., Technical Report of IEICE, SDM-93-24, ICD93-26, pp. 15-20.
"A Semiconductor MOS Memory and a Usage Thereof", Yasoji Suzuki, pp. 90-93, Nikkan Kogyo Shinbunsha.

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