Scalable gate and storage dielectric

Details Scalable gate and storage dielectric Scalable gate and storage dielectric

2006-02-14

2006-02-14

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S410000, C257S411000, C438S216000, C438S287000, C438S591000

Reexamination Certificate

active

06998667

ABSTRACT:
Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

REFERENCES:
patent: 4566173 (1986-01-01), Gossler et al.
patent: 4870470 (1989-09-01), Bass et al.
patent: 6207589 (2001-03-01), Ma et al.
patent: 6245606 (2001-06-01), Wilk et al.
patent: 6368919 (2002-04-01), Nuttall et al.
patent: 6391724 (2002-05-01), Park
patent: 6417570 (2002-07-01), Ma et al.
patent: 6444545 (2002-09-01), Sadd et al.
patent: 6445030 (2002-09-01), Wu et al.
patent: 6492283 (2002-12-01), Raaijmakers et al.
patent: 6521945 (2003-02-01), Nuttall et al.
patent: 6559014 (2003-05-01), Jeon
patent: 6579767 (2003-06-01), Park et al.
patent: 6586349 (2003-07-01), Jeon et al.
patent: 6617639 (2003-09-01), Wang et al.
patent: 6642573 (2003-11-01), Halliyal et al.
patent: 6645882 (2003-11-01), Halliyal et al.
patent: 6700771 (2004-03-01), Bhattacharyya
patent: 2002/0190302 (2002-12-01), Bojarczuk et al.
U.S. Appl. No. 09/944,986, filed Aug. 30, 2001, Bhattacharyya.
J. H. Lee et al., “Effect of Polysilicon Gate on the Flatband Voltage Shift and Mobility Degradation for ALD-AL2O3 Gate Dielectric,” IEDM Technical Digest, San Francisco, Dec. 10-13, 2000, pp. 645-648.
L. Manchanda et al., “Si-Doped Aluminates for High Temperature Metal-Gate CMOS: Zr-Al-Si-O, A Novel Gate Dielectric for Low Power Applications,” IEDM Technical Digest, San Francisco, Dec. 10-13, 2000, pp. 23-26.
A. Bhattacharyya et al., “Physical and Electrical Characteristics of LPCVD Silicon Rich Nitride,” ECS Digest, New Orleans, 1984.
D. A. Buchanan et al., “80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications,” IEDM Technical Digest, San Francisco, Dec. 10-13, 2000, pp. 223-226.
Byoung Hun Lee et al., “Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternate Gate Dielectric Application,” IEDM Technical Digest, Washington DC, Dec. 5-8, 1999, pp. 133-136.
Wen-Jie Qi et al., “MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si,” IEDM Technical Digest, Dec. 5-8, 1999, pp. 145-148.
H. F. Luan et al., “High Quality Ta2O5 Gate Dielectric with Tox,eq < 10A,” IEDM Technical Digest, Dec. 5-8, 1999, pp. 141-144.
K. Hieda et al., “Low Temperature (Ba, Sr) TiO3 Capacitor Process Integration (LTB) Technology for Gigabit Scaled DRAMs,” IEDM Technical Digest, Dec. 5-8, 1999, pp. 789-792.
G. B. Alers et al., “Advanced Amorphous Dielectrics for Embedded Capacitors,” IEDM Technical Digest, Dec. 5-8, 1999, pp. 797-800.
Xin Guo et al., “High Quality Ultra-thin (1.5 nm) TiO2/Si3N4 Gate Dielectric for Deep Sub-micron CMOS Technology,” IEDM Technical Digest, Dec. 5-8, 1999, pp. 137-140.
H.-J. Gossman et al., “Doping of Si thin films by low-temperature molecular beam epitaxy,” J. Appl. Phys. 73, Jun. 16, 1993, pp. 8237-8241.
J. Wolcik et al., “Characterization of Silicon Oxynitride Thin Films Deposited by ECR-PECVD,” Tenth Canadian Semiconductor Technology Conference, Ottawa, Canada, Aug. 13-17, 2001, p. 184.
Adrian J. Devasahayam et al., “Material Properties of Ion Beam Deposited Oxides for the Opto-Electronic Industry,” Tenth Canadian Semiconductor Technology Conference, Ottawa, Canada, Aug. 13-17, 2001, p. 185.

Affiliated with

Also associated with

Rating

Scalable gate and storage dielectric does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scalable gate and storage dielectric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable gate and storage dielectric will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3665706