Test region layout for shallow trench isolation

Details Test region layout for shallow trench isolation Test region layout for shallow trench isolation

2006-02-21

2006-02-21

Lee, Hsien-Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S414000, C257S618000, C438S014000, C438S016000

Reexamination Certificate

active

07002177

ABSTRACT:
A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

REFERENCES:
patent: 6476920 (2002-11-01), Scheiner et al.
patent: 6859748 (2005-02-01), Yang et al.
patent: 2002/0043683 (2002-04-01), Nakagawa et al.
patent: 2002/0123872 (2002-09-01), Okada

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