History FIFO with bypass wherein an order through queue is...

Details History FIFO with bypass wherein an order through queue is... History FIFO with bypass wherein an order through queue is...

2006-10-03

2006-10-03

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S052000, C710S053000, C710S054000, C710S057000, C710S306000, C710S309000, C710S317000

Reexamination Certificate

active

07117287

ABSTRACT:
An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

REFERENCES:
patent: 5699530 (1997-12-01), Rust et al.
patent: 5796413 (1998-08-01), Shipp et al.
patent: 6092128 (2000-07-01), Maas et al.
patent: 6487627 (2002-11-01), Willke et al.
patent: 6614798 (2003-09-01), Bishop et al.
patent: 6801976 (2004-10-01), Creta et al.
patent: 6804750 (2004-10-01), LaBerge
patent: 6912612 (2005-06-01), Kapur et al.
patent: 2004/0022094 (2004-02-01), Radhakrishnan et al.
patent: 2004/0064626 (2004-04-01), Shah et al.
patent: 2004/0107240 (2004-06-01), Zabarski et al.
http://wombat.doc.ic.ac.uk/foldoc/, definition of “Circular Buffer”, Jun. 17, 2000.
Rajpal, et al; “Operating FIFOs On Full and Empty Boundary Conditions”; Integrated Device Technology, Inc.; Mar. 1999.
“Bus Matching with IDT FIFOs”; Integrated Device Technology; Apr. 2001.
“CMOS Asynchronous FIFO 256×9, 512×9 and 1,024×9”; Integrated Device Technology, Inc.; Sep. 2002.

Affiliated with

Also associated with

Rating

History FIFO with bypass wherein an order through queue is... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with History FIFO with bypass wherein an order through queue is..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and History FIFO with bypass wherein an order through queue is... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3663163