Vertical DRAM and fabrication method thereof

Details Vertical DRAM and fabrication method thereof Vertical DRAM and fabrication method thereof

2006-11-14

2006-11-14

Owens, Douglas W. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000, C257S303000, C257S304000, C257S305000, C257S905000, C257S906000, C257S908000

Reexamination Certificate

active

07135731

ABSTRACT:
A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

REFERENCES:
patent: 5519236 (1996-05-01), Ozaki
patent: 5937296 (1999-08-01), Arnold
patent: 6163045 (2000-12-01), Mandelman et al.
patent: 6236079 (2001-05-01), Nitayama et al.
patent: 6420228 (2002-07-01), Roesner et al.
patent: 6437388 (2002-08-01), Radens et al.
patent: 6552382 (2003-04-01), Wu
patent: 6605838 (2003-08-01), Mandelman et al.
patent: 6747306 (2004-06-01), Dyer

Affiliated with

Also associated with

Rating

Vertical DRAM and fabrication method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical DRAM and fabrication method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical DRAM and fabrication method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3657645