Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2006-02-07

2006-02-07

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S202000, C257S204000, C257S206000, C257S315000, C257S316000, C257S909000, C257SE27078

Reexamination Certificate

active

06995436

ABSTRACT:
In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged in the column direction to constitute a sub array, and the sub arrays arranged in the column direction are arranged in parallel or axisymmetically in the row direction. With this arrangement, the substrate contact region, the well contact region, and the diffusion region of the PMOS transistor can be shared between the adjacent memory cells, thereby reducing the area of the cell array.

REFERENCES:
patent: 6204541 (2001-03-01), Togami et al.
McPartland, Richard J., et al., “1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications”, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 158-161.

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