Vertically wired integrated circuit and method of fabrication

Details Vertically wired integrated circuit and method of fabrication Vertically wired integrated circuit and method of fabrication

2006-10-10

2006-10-10

Smith, Bradley K. (Department: 2891)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000, C257SE21540

Reexamination Certificate

active

07118988

ABSTRACT:
A static random access memory (SRAM) cell structure is created in a three-dimensional format as a vertical stack of wired transistors. These transistors are fabricated from crystalline silicon, and supplemental wiring structure features are fabricated to comprise a circuit along the walls of a vertical pillar. The three-dimensional cell integrated circuit can be created by a single mask step. Various structural features and methods of fabrication are described in detail. Peripheral interface, a two pillar version and other supplemental techniques are also described.

REFERENCES:
patent: 4876223 (1989-10-01), Yoda et al.
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5266526 (1993-11-01), Aoyama et al.
patent: 5328810 (1994-07-01), Lowrey et al.

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