Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-05
2006-12-05
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07146599
ABSTRACT:
A method is disclosed for conducting optical proximity correction (OPC) on at least two features in a circuit design. After detecting a first feature having at least one end thereof to be in the proximity of one end of a second feature, a first OPC pattern is incorporated to the end of the first feature toward a first direction; and a second OPC pattern is incorporated to the end of the second feature toward a second direction that is substantially opposite from the first direction.
REFERENCES:
patent: 6189136 (2001-02-01), Bothra
patent: 6303253 (2001-10-01), Lu
patent: 6631307 (2003-10-01), Tzu et al.
patent: 6670081 (2003-12-01), Laidig et al.
patent: 6673638 (2004-01-01), Bendik et al.
patent: 6753115 (2004-06-01), Zhang et al.
patent: 6875545 (2005-04-01), Eurlings et al.
patent: 2004/0107410 (2004-06-01), Misaka et al.
patent: 2005/0022150 (2005-01-01), Liu et al.
Duane Morris LLP
Garbowski Leigh M.
Taiwan Semiconductor Manufacturing Co. Ltd.
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