Pass through circuit for reduced memory latency in a...

Details Pass through circuit for reduced memory latency in a... Pass through circuit for reduced memory latency in a...

2006-02-28

2006-02-28

Perveen, Rehana (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

Reexamination Certificate

active

07007125

ABSTRACT:
A technique and mechanism for reducing memory latency asymmetry in a multiprocessor system by replacing one (or more) processors with a bypass or pass-through device. Using the pass-through mechanism, the reduced number of processors in the system enables all of the remaining processors to connect to each other directly using the interconnect links. The reduction in processor count improves symmetry and reduces overall latency thereby potentially improving performance of certain applications despite having fewer processors. In one specific implementation, the pass through device is used to connect two HyperTransport links together where each of the links is connected to a processor at the other end.

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