Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-21
2006-02-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07003741
ABSTRACT:
A method for optimal driver selection uses a cost function that is based on the non-linear delay characteristics and the stage gain of the candidate drivers. The cost function operates to select an optimal driver for driving the predetermined capacitive load which. simultaneously minimizes the delay and the amount of input capacitance introduced. In one embodiment, a method for selecting a driver for driving a load capacitance from a group of drivers includes: computing for each driver a cost based on a cost function associated with the driver, and selecting the driver having the smallest cost. The cost function is directly proportional to a delay of the driver and inversely proportional to the logarithm of a stage gain of the driver. In another embodiment, the stage gain is an output capacitance driven by the driver (the load capacitance) divided by an input capacitance of the driver.
REFERENCES:
patent: 5666290 (1997-09-01), Li et al.
patent: 5880567 (1999-03-01), Browne
patent: 6609228 (2003-08-01), Bergeron et al.
patent: 6754877 (2004-06-01), Srinivasan
Bowers Brandon
Kwok Edward C.
MacPherson Kwok & Chen & Heid LLP
Sequence Design, Inc.
Siek Vuthe
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