Managing processor architected state upon an interrupt

Details Managing processor architected state upon an interrupt Managing processor architected state upon an interrupt

2006-10-03

2006-10-03

Padmanabhan, Mano (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

07117319

ABSTRACT:
A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.

REFERENCES:
patent: 4484274 (1984-11-01), Berenbaum et al.
patent: 5057997 (1991-10-01), Chang et al.
patent: 5987495 (1999-11-01), Ault et al.
patent: 6026471 (2000-02-01), Goodnow et al.
patent: 6189112 (2001-02-01), Slegel et al.
patent: 6247109 (2001-06-01), Kleinsorge et al.
patent: 6308290 (2001-10-01), Forlenza et al.
patent: 6981083 (2005-12-01), Arimilli et al.
patent: PUPA S60-027031 (1985-02-01), None
patent: PUPA S60-164840 (1985-08-01), None
patent: PUPA S61-241838 (1986-10-01), None
patent: PUPA H03-201032 (1991-09-01), None
patent: PUPA H04-288625 (1992-10-01), None

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