Programmable logic device including multipliers and...

Details Programmable logic device including multipliers and... Programmable logic device including multipliers and...

2006-11-28

2006-11-28

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000, C708S625000, C708S523000, C714S726000, C714S724000, C714S725000

Reexamination Certificate

active

07142010

ABSTRACT:
In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4799004 (1989-01-01), Mori
patent: 4839847 (1989-06-01), Laprade
patent: 4871930 (1989-10-01), Wong et al.
patent: 4912345 (1990-03-01), Steele et al.
patent: 4967160 (1990-10-01), Quievy et al.
patent: 4982354 (1991-01-01), Takeuchi et al.
patent: 4994997 (1991-02-01), Martin et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5128559 (1992-07-01), Steele
patent: 5371422 (1994-12-01), Patel et al.
patent: 5381357 (1995-01-01), Wedgwood et al.
patent: 5483178 (1996-01-01), Costello et al.
patent: 5563819 (1996-10-01), Nelson
patent: 5636150 (1997-06-01), Okamoto
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5696708 (1997-12-01), Leung
patent: 5754459 (1998-05-01), Telikepalli
patent: 5761483 (1998-06-01), Trimberger
patent: 5777912 (1998-07-01), Leung et al.
patent: 5812562 (1998-09-01), Baeg
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 5880981 (1999-03-01), Kojima et al.
patent: 5931898 (1999-08-01), Khoury
patent: 5968196 (1999-10-01), Ramamurthy et al.
patent: 5991898 (1999-11-01), Rajski et al.
patent: 6064614 (2000-05-01), Khoury
patent: 6066960 (2000-05-01), Pedersen
patent: 6069487 (2000-05-01), Lane et al.
patent: 6091261 (2000-07-01), De Lange
patent: 6097988 (2000-08-01), Tobias
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6130554 (2000-10-01), Kolze et al.
patent: 6157210 (2000-12-01), Zaveri et al.
patent: 6163788 (2000-12-01), Chen et al.
patent: 6167415 (2000-12-01), Fischer et al.
patent: 6175849 (2001-01-01), Smith
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6243729 (2001-06-01), Staszewski
patent: 6246258 (2001-06-01), Lesea
patent: 6279021 (2001-08-01), Takano et al.
patent: 6286024 (2001-09-01), Yano et al.
patent: 6314551 (2001-11-01), Borland
patent: 6321246 (2001-11-01), Page et al.
patent: 6323680 (2001-11-01), Pedersen et al.
patent: 6359468 (2002-03-01), Park et al.
patent: 6367003 (2002-04-01), Davis
patent: 6407576 (2002-06-01), Ngai et al.
patent: 6407694 (2002-06-01), Cox et al.
patent: 6480980 (2002-11-01), Koe
patent: 6483343 (2002-11-01), Faith et al.
patent: 6542000 (2003-04-01), Black et al.
patent: 6574762 (2003-06-01), Karimi et al.
patent: 6591283 (2003-07-01), Conway et al.
patent: 6600788 (2003-07-01), Dick et al.
patent: 6700581 (2004-03-01), Baldwin et al.
patent: 6728901 (2004-04-01), Rajski et al.
patent: 6745254 (2004-06-01), Boggs et al.
patent: 6904471 (2005-06-01), Boggs et al.
patent: 2002/0089348 (2002-07-01), Langhammer
patent: 2004/0064770 (2004-04-01), Xin
patent: 2004/0083412 (2004-04-01), Corbin et al.
patent: 2004/0193981 (2004-09-01), Clark et al.
patent: 0 461 798 (1991-12-01), None
patent: 0 555 092 (1993-08-01), None
patent: 0 909 028 (1999-04-01), None
patent: 0 927 393 (1999-07-01), None
patent: 1 220 108 (2002-07-01), None
patent: 2 283 602 (1995-05-01), None
patent: 07-135447 (1995-05-01), None
patent: WO 97/08606 (1997-03-01), None
patent: WO 00/52824 (2000-09-01), None
patent: WO01/13562 (2001-02-01), None
Altera Corporation, “Implementing Multipliers in FLEX 10K EABs,” Mar. 1996.
Xilinx, Inc., “Xilinx Unveils New FPGA Architecture to Enable High-Performance, 10 Million System Gate Designs,” Jun. 22, 2000.
Xilinx, Inc., “Xilinx Announces DSP Algorithms, Tools and Features for Virtex-II Architecture,” Nov. 21, 2000.
Xilinx, Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays,” module 2 of 4, Jan. 25, 2001.
Xilinx, Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays,” module 1 of 4, Apr. 2, 2001.
Xilinx, Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays,” Apr 2, 2001, module 2 of 4.
Altera Corporation, “Implementing Logic with the Embedded Array in FLEX 10K Devices,” ver. 2.1, May 2001.
QuickLogic Corporation, “The QuickDSP Design Guide,” revision B, Aug. 2001.
QuickLogic Corporation, “QuickDSP™ Family Data Sheet,” revision B, Aug. 7, 2001.
Traika, C., “Embedded digital signal processor (DSP) modules in programmable logic devices (PLDs),”Elektronik, vol. 49, No. 14, Jul. 11, 2000, pp. 84-96.
Berg. B.L., et al.“Designing Power and Area Efficient Multistage FIR Decimators with Economical Low Order Filters,”ChipCenter Technical Note, Dec. 2001.
Gaffar, A.A., et al., “Floating-Point Bitwidth Analysis via Automatic Differentiation,”IEEE Conference on Field Programmable Technology, Hong Kong, Dec. 2001.
Huang, J., et al., “Simulated Performance of 1000BASE-T Receiver with Different Analog Front End Designs,”Proceedings of the 35th Asilomar Conference on Signals, Systems, and Computers, Nov. 4-7, 2001.
Lattice Semiconductor Corp,ORCA® FPGA Express™ Interface Manual; IsoLEVER® Version 3.0, 2002.
Lucent Technologies, Microelectronics Group,“Implementing and Optimizing Multipliers in ORCA™ FPGAs,”, Application Note AP97-008FGPA, Feb. 1997.
Xiilnx, Inc., “A 1D Systolic FIR,” copyright 1994-2002, downloaded from http://www.iro.umontreal.ca/˜aboulham/F6221/Zilinx%20A%201D%20systolic%20FIR.htm.
Xilinx, Inc., “The Future of FPGA's,” White Paper, available Nov. 14, 2005 for download from http://www.xilinx.com/prs—rls,5yrwhite.htm.
Valls, J., et al., “A Study About FPGA-Based Filters,”Signal Processing Systems, 1998, SIPS 98, 1998 IEEE Workshop, Oct. 10, 1998, pp. 192-201.

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