Semiconductor integrated circuit designing apparatus,...

Details Semiconductor integrated circuit designing apparatus,... Semiconductor integrated circuit designing apparatus,...

2006-11-21

2006-11-21

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C702S191000

Reexamination Certificate

active

07139989

ABSTRACT:
In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a predetermined range, while a logic gate in the circuit block is selected when the amount of noise is out of the predetermined range and a bypass condenser is added to the selected logic gate. Therefore, a bypass condenser having a required capacitance can be added in the vicinity of a noise source in the circuit block, whereby the noise can be reliably restricted to the predetermined range.

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Chen, Howard H., et al., “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design” Watson Research Center, Yorktown Heights, NY 10598, U.S.A., pp. 636-643.

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