Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-02-14
2006-02-14
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S945000, C438S962000
Reexamination Certificate
active
06998333
ABSTRACT:
A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.
REFERENCES:
patent: 5045408 (1991-09-01), Williams et al.
patent: 5972744 (1999-10-01), Morimoto et al.
patent: 6010934 (2000-01-01), Wu
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6286226 (2001-09-01), Jin
patent: 6413880 (2002-07-01), Baski et al.
patent: 6509619 (2003-01-01), Kendall et al.
patent: 6515339 (2003-02-01), Shin et al.
patent: 6699779 (2004-03-01), Chen et al.
patent: 6707098 (2004-03-01), Hofmann et al.
patent: 6773616 (2004-08-01), Chen et al.
patent: 2002/0024065 (2002-02-01), Lee et al.
Yong Chen, et al.; “Nanowires of Four Epitaxial Hexagonal Silicides Grown on SI(001)”; Mar. 1, 2002; Journal of Applied Physics, pp. 3213-3218.
Yong Chen, et al.; “Self-Assembled Growth of Epitaxial Erbium Disilicide Nanowires of Silicon (001)”; Jun. 26, 2000; Applied Physics Letters, vol. 76, No. 26.
Kakushima, K., et al.; “Fabrication of Various Shapes Nano Structure Using SI Anisotropic Etching and Silicidation”; 2001; 11THInternational Conference on Solid State Sensors and Actuators, Munich, Germany.
A. Dutta, et al.;“Silicon-Based-Single-Electron Memory Using a Multiple-Tunnel JunctionFabricated by Electron-Beam Direct Writing”;Sep. 6, 1999; Applied Physics Letters, vol. 75 No. 10.
Yong Chen, et al.; Self-Assembled Rare-Earth Silicide Nanowires on SI(001); May 29, 2001 Physical Review B, vol. 63, 4 pages.
Chen Yong
Williams R. Stanley
LandOfFree
Method for making nanoscale wires and gaps for switches and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making nanoscale wires and gaps for switches and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making nanoscale wires and gaps for switches and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3646274