Memory address repair without enable fuses

Details Memory address repair without enable fuses Memory address repair without enable fuses

2006-10-03

2006-10-03

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

07116590

ABSTRACT:
A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

REFERENCES:
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patent: 5732029 (1998-03-01), Lee et al.
patent: 5798974 (1998-08-01), Yamagata
patent: 6317370 (2001-11-01), Shirley

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