Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-11-21
2006-11-21
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S205000, C365S210130
Reexamination Certificate
active
07139196
ABSTRACT:
A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.
REFERENCES:
patent: 4761765 (1988-08-01), Hashimoto
patent: 5191552 (1993-03-01), Nakai et al.
patent: 5717640 (1998-02-01), Hashimoto
patent: 5748530 (1998-05-01), Gotou et al.
patent: 5773997 (1998-06-01), Stiegler
patent: 5774405 (1998-06-01), Tomishima
patent: 5856748 (1999-01-01), Seo et al.
patent: 5995421 (1999-11-01), McKenny
patent: 6002614 (1999-12-01), Banks
patent: 6026052 (2000-02-01), Fukutani et al.
patent: 6081453 (2000-06-01), Iwahashi
Dinh Son T.
DLA Piper (US) LLP
Silicon Storage Technology, Inc.
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