Solid-state imaging device and method for manufacturing same

Details Solid-state imaging device and method for manufacturing same Solid-state imaging device and method for manufacturing same

2006-05-16

2006-05-16

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S023000

Reexamination Certificate

active

07045400

ABSTRACT:
The reduction in size, noise and voltage is realized in a MOS solid-state imaging device. A gate electrode in a pixel part is formed in a two-level structure. An amplifier gate of an amplifier transistor is formed in the first level while a select gate of a select transistor is formed in the second level. The both are structurally partly overlapped. With the first-level amplifier gate as self-alignment, ions are implanted for a select gate in the second level. Although the gate electrode if formed in one level as in the conventional requires a space of nearly a design rule between the amplifier gate and the select gate, the structure of the invention can eliminate such a dead space. Meanwhile, because the diffusion layer does not exist between the amplifier gate and the select gate, the diffusion layer is eliminated of sheet resistance and voltage drop. Also, the resistance and voltage decrease, resulting from the LDD region of a transistor gate end, are eliminated in one end of the amplifier gate and in one end of the select gate.

REFERENCES:
patent: 6822306 (2004-11-01), Mabuchi
patent: 2003/0122131 (2003-07-01), Zhang et al.

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