Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2006-06-27
2006-06-27
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S080000, C326S081000
Reexamination Certificate
active
07068075
ABSTRACT:
A multi-level voltage output control circuit selectively outputs one of multi-level power voltages by driving gates of two MOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, the two output signals having complementary phases to each other and generated from two logic gates receiving two input signals which have an identical timing and complementary phases to each other, wherein the two logic gates advance or slow down a rising timing and/or a falling timing of the two output signals by differently adjusting a size of PMOS transistors and that of NMOS transistors, which construct the logic gates, thereby excluding a case in which the two output signals are in a same logic state at the same time.
REFERENCES:
patent: 4408135 (1983-10-01), Yuyama et al.
patent: 5747979 (1998-05-01), Nagai
patent: 6133748 (2000-10-01), Ternullo, Jr.
patent: 6826096 (2004-11-01), Pekny et al.
Sedra/Smith, Microelectronic Cirucits, 4th Ed. 1998, Translated Paper 2001, 2 pages, fig. 13.16 and 13.17, no month.
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Tran Anh Q.
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