Method and apparatus for determining transistor sizes

Details Method and apparatus for determining transistor sizes Method and apparatus for determining transistor sizes

2006-10-24

2006-10-24

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07127687

ABSTRACT:
A method of determining at least one ratio of transistor sizes. The method includes creating a sizing model by replacing at least one logic element in a circuit description with a sizing element that includes a piece-wise-linear current source. The method also includes determining a steady state solution to the sizing mode and determining at least one ratio of transistor sizes from the steady state solution. The method may also include determining at least one dimension of a transistor based at least in part upon the ratio of transistor sizes.

REFERENCES:
patent: 5446676 (1995-08-01), Huang et al.
patent: 5880967 (1999-03-01), Jyu et al.
patent: 6629301 (2003-09-01), Sutherland et al.
patent: WO 200223409 (2002-03-01), None
Berkelaar et al., Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with piecewise linear simulator','IEEE Transaction on Computer-Aided Design, vol. 15, pp. 1424-1414.
Sutherland et al., Logical Effort Designing Fast CMOS Circuits, 1999.

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