Dynamic memory word line driver scheme

Details Dynamic memory word line driver scheme Dynamic memory word line driver scheme

2006-05-02

2006-05-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S149000, C365S150000, C365S189120, C365S230010

Reexamination Certificate

active

07038937

ABSTRACT:
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vssand Vdd, and for providing a select signal at levels Vssand Vdd, a high voltage supply source Vppwhich is higher in voltage than Vdd, a circuit for translating the select signals at levels Vssand Vddto levels Vssand Vppand for applying it directly to the word lines whereby an above Vddvoltage level word line is achieved without the use of double boot-strap circuits.

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