Stacked gate semiconductor memory

Details Stacked gate semiconductor memory Stacked gate semiconductor memory

2006-06-27

2006-06-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000

Reexamination Certificate

active

07067871

ABSTRACT:
A semiconductor memory embraces a plurality of memory cell transistors, and each of the memory cell transistors encompasses a substrate; a gate insulator stacked on the substrate, configured to enable tunneling of electrons through the gate insulator; a floating gate electrode stacked on the gate insulator, configured to accumulate electron charges; an inter-electrode dielectric stacked on the floating gate electrode incorporating a positive charge layer, distribution of the positive charge layer being localized in the lower half of the inter-electrode dielectric; and a control gate electrode stacked on the inter-electrode dielectric.

REFERENCES:
patent: 5869858 (1999-02-01), Ozawa et al.
patent: 5990515 (1999-11-01), Liu et al.
patent: 08-316348 (1996-11-01), None
U.S. Appl. No. 10/724,103, filed Dec. 1, 2003, Yoshio Ozawa et al.
W. -H. Lee et al., “A Novel High K Inter-Poly Dielectric(IPD), A12O3for Low Voltage/High Speed Flash Memories: Erasing in msecs at 3.3V”, Symposium on VLSI Technology Digest of Technical Papers: p. 117-118, (Jun. 10-12, 1997).

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