Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2006-06-06

2006-06-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185290

Reexamination Certificate

active

07057936

ABSTRACT:
A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.

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