Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-10-17
2006-10-17
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
07124351
ABSTRACT:
A method of calculating a Cyclic Redundancy Check (CRC) value for a multi-bit input data word, using a defined generator polynomial is disclosed. The method includes the steps of: serially shifting at least a portion of the input data word into a register; XORing the contents of the register with the generator polynomial if the LSB of the register is ‘1’; shifting the contents of the register right by one position; shifting into the MSB position of the register a new bit of the input data word, having been XORed with the LSB of the register; repeating the previous step for all message data bits; shifting into the register a number of ‘0’s equal to the length of the generator polynomial; reading from the register the calculated CRC value. Apparatus for performing the method is also disclosed.
REFERENCES:
patent: 5517512 (1996-05-01), Saegusa
patent: 6192498 (2001-02-01), Arato
patent: 6530057 (2003-03-01), Kimmitt
patent: 6820232 (2004-11-01), Kim et al.
patent: 6836869 (2004-12-01), Wyland
Aldridge Christopher
Lee Chong Yee
Pradhan Mridula
Iannucci Robert
Jorgenson Lisa K.
National University of Singapore
Seed IP Law Group PLLC
STMicroelectronics Asia Pacific Pte. Ltd.
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